1. Field of the Invention
The invention relates in general to a gate structure of a semiconductor device and methods of forming a word line structure and a memory, and more particularly to a gate structure of a semiconductor device and methods of forming a word line structure and a memory capable of increasing a current of a memory cell.
2. Description of the Related Art
In order to satisfy the requirement in the reduction of size of a semiconductor element, the integration of the semiconductor element may be increased. However, increasing the integration to reduce the size of a memory tends to be limited due to the array structure of the memory.
In a NAND array memory, for example, a dopant is implanted between upper and lower adjacent memory cells to form a doped region, so that the doped region is served as a drain or a source. FIG. 1 (Prior Art) is a schematic illustration showing a conventional NAND array memory. As shown in FIG. 1, the NAND array memory 40 has word lines 400, each of which includes a dielectric layer 420, a conductive layer 430 and a mask layer 440 sequentially disposed on a substrate 410. The position where a dopant 450 is implanted is between the adjacent word lines 400. If an interval D between the adjacent word lines 400 is reduced in order to increase the integration of the memory 40, the dopant 450 may not be implanted due to the limitation of the apparatus.
Furthermore, when the integration of the memory is increased, the memory generally tends to encounter the condition of the short channel effect (SCE) and the condition that the current of the memory cell is insufficient. Thus, it is an important subject for the related industries to provide a memory capable of satisfying the requirement in the size and the integration while increasing the current of the memory cell.